module sim_2(
);

reg clk,rst_n;
initial
begin
    rst_n = 1; 
    #20; rst_n = 0;
    #20; rst_n = 1;
    clk = 1; forever #5 clk = ~clk;
end


parameter CMD_Reset =               8'hFF;
parameter CMD_ReadID =              8'h90;
parameter CMD_ReadStatus =          8'h70;
parameter CMD_ReadPage_C0 =         8'h00;
parameter CMD_ReadPage_C1 =         8'h30;
parameter CMD_ReadPageCache =       8'h31;
parameter CMD_ReadPageCacheCast =   8'h3f;
parameter CMD_ReadMul_C0 =          8'h00;
parameter CMD_ReadMul_C1 =          8'h32;
parameter CMD_ProgPage_C0 =         8'h80;
parameter CMD_ProgPage_C1 =         8'h10;
parameter CMD_ProgPageCache_C0 =    8'h80;
parameter CMD_ProgPageCache_C1 =    8'h15;
parameter CMD_ProgPageMul_C0 =      8'h80;
parameter CMD_ProgPageMul_C1 =      8'h11;
parameter CMD_EraseBlock_C0 =       8'h60;
parameter CMD_EraseBlock_C1 =       8'hD0;
parameter CMD_EraseMul_C0 =         8'h60;
parameter CMD_EraseMul_C1 =         8'hD1;

parameter State_command =   3'b000;
parameter State_adderss =   3'b001;
parameter State_WriteData = 3'b010;
parameter State_ReadData  = 3'b011;
parameter State_Idle =      3'b100;

wire clk_m;
wire ready;
wire[2:0] cmd_m;
reg[2:0] cmd_r;
assign cmd_m = cmd_r;

reg O_DQS;
wire[7:0] data_m;
wire I_dqs;
wire dqs_m;
wire[7:0] dq_m;
wire dv_m;
wire[7:0] val_m;
reg[7:0] data_r;
reg    oe;
assign I_dqs = dqs_m;
assign data_m = data_r;
assign dqs_m = oe ? O_DQS : 1'bz;
wire[7:0] O_DQ;
reg[7:0]  I_DQ;
assign O_DQ = dq_m;
assign dq_m = oe ? I_DQ : 8'hzz;

reg[31:0] DataNum;
reg[31:0] Datacounter;

Sync_port u_Sync_port(
//	.CE_s      (CE_s     ),
    .CLK       (clk_m    ),
    .WR        (WR       ),
    .CLE       (cle_m    ),
    .ALE       (ale_m    ),
    .DQ        (dq_m     ),
    .DQS       (dqs_m    ),
    .RB        (RB       ),
    .WP_s      (WP_s     ),

    .clkX2          (clk        ),
    .rst_n          (rst_n      ),
    .en             (1'b1       ),
    .Cmd            (cmd_m      ),
    .InputVal       (data_m     ),
    .IV_En          (ready      ),
    .ReadVal        (val_m      ),
    .RV_En          (dv_m       ),
    .RB_n           (RB_n       ),
    .RWDataNum      (DataNum    ),
    .RWDataCounter  (Datacounter)
);

reg[7:0] counter1;
reg[7:0] counter2;
reg s1;
reg s2;
reg s3;
reg s4;
wire clk1;
wire clk2;
wire clk3;
wire clk4;
assign clk1 = clk & s1;
assign clk2 = clk & s2;
assign clk3 = clk & s3;
assign clk4 = clk & s4;

always @(negedge clk1 or negedge rst_n) begin
    if (rst_n) begin
        if (counter1 < 8'ha4) begin
            cmd_r <= State_adderss;
            if (ready) begin
                data_r <= counter1;
                counter1 <= counter1 + 1'b1;
            end else begin
                data_r <= data_r;
                counter1 <= counter1;
            end
       end else begin
            s1 <= 1'b0;
            s2 <= 1'b1;
            cmd_r <= State_Idle;          
       end 
    end else begin
        s1 <= 1'b1;
        s2 <= 1'b0;
        counter1 <= 8'ha0;
        cmd_r <= State_Idle;
    end
end

always @(negedge clk2 or negedge rst_n) begin
    if (rst_n) begin
        if (counter2 < 8'hc3) begin
            cmd_r <= State_command;
            if (ready) begin
                data_r <= counter2;
                counter2 <= counter2 + 1'b1; 
            end else begin
                data_r <= data_r;
                counter2 <= counter2;
            end
        end else begin
            s2 <= 1'b0;
            s3 <= 1'b1;
            cmd_r <= State_Idle;
            
        end
    end else begin
        counter2 <= 8'hc0;
        s3 <= 1'b0;
    end
end

reg[7:0] counter3;
always @(negedge clk3 or negedge rst_n) begin
    if (rst_n) begin
        if (counter3 <= 8'hdf) begin
            cmd_r <= State_WriteData;
            if (ready) begin
                data_r <= counter3;
                counter3 <= counter3 + 1'b1;
                Datacounter <= Datacounter + 1'b1;
            end else begin
                data_r <= data_r;
                counter3 <= counter3;
            end
        end else begin
            cmd_r <= State_Idle;
            s3 <= 1'b0;
            s4 <= 1'b1;
            Datacounter <= 8'h00;
        end
    end else begin
        Datacounter <= 8'h00;
        DataNum <= 8'h10;
        counter3 <= 8'hd0;
        s4 <= 1'b0;
    end
end

reg[7:0] readed;
always @(negedge clk4 or negedge rst_n) begin
    if (rst_n) begin
        cmd_r <= State_ReadData;
        if (dv_m) begin
            readed <= val_m;
            Datacounter <= Datacounter + 1'b1;
            if(Datacounter == 8'h10)
                s4 <= 1'b0;
        end else begin
            readed <= readed;
        end
    end else begin
        readed <= readed;
    end
end

reg[7:0] delayCounter;
reg[7:0] outData;
always @(posedge clk4 or negedge rst_n) begin
    if (rst_n) begin
        if (delayCounter == 8'h00) begin
            oe <= 1'b1;
            O_DQS <= ~O_DQS;
            I_DQ <= outData;
            outData <= outData - 1'h1;
        end else begin
            delayCounter <= delayCounter - 1'b1;
        end
    end else begin
        delayCounter <= 8'h05;
        outData <= 8'hff;
        O_DQS <= 1'b0;
        oe <= 1'b0;
    end
end

endmodule // sim_2